`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2017/10/29 17:12:36
// Design Name: 
// Module Name: v1
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module vga1(
    input clk,
    input clk_adc,
    input rst_n,
    input [11:0] sample1,
    input [11:0] sample2,
    input [31:0] tcnt,
    input vppset,
    //input [0:1055] imgbuf [0:623],  //鐏炲繐绠烽悽璇茬
    output Hsync,
    output Vsync,
    output [3:0] vgaRed,
    output [3:0] vgaGreen,
    output [3:0] vgaBlue
);                                                              
parameter  ta=80,tb=160,tc=800,td=40,te=1056,to=3,tp=21,tq=600,tr=1,ts=624;  
reg[10:0] x_counter=0;                           
reg[10:0] y_counter=0;
reg [11:0] colour;
wire clk_vga;

reg showing_frame;
reg[31:0] cnt1=0;
reg[31:0] cnt=0;
reg[11:0] wave1[0:2048-1];
reg[11:0] wave2[0:2048-1];
//閻樿鎷�?閿熻棄鍨忛幑銏犲綁閿燂拷?
reg acq_valid = 0,acq_ready = 0;


reg [6:0] font_addr=7'b0;
wire [127:0] fchar;
//    assign led=sw;   




clk_wiz_0 uut_clk                          
(
    .clk_in1(clk),
    .clk_out1(clk_vga)
);
     



// always @(posedge clk or negedge rst_n) 
// begin   
//     if(!rst_n)
//     begin
//         cnt = 0;
//         acq_ready = 1;

//     end
//     else begin 
//         //ready 閻樿鎷�?閿熸垝绗杁ata閺堝鏅ラ崣顖欎簰鐎涙ê鍋�
//         if (acq_ready==1) 
//             if (clk_adc==1)
//             begin
//                 wave1[cnt1] <= sample1;
//                 wave2[cnt1] <= sample2;
//                 cnt = cnt + 1;
//                 if(cnt >= 2048) begin
//                     cnt = 0;
//                     //1---闁插洭娉︾€瑰本鍨氶敓锟�?閸氼垱澹傞幓蹇撴綏閿燂拷?
//                     acq_ready = 0;  //闁插洦鐗辩€瑰本鍨�

//                 end
//             end
//         //ready 閺堫亣绻樼悰宀勫櫚閿燂拷?
//         else if(acq_ready==0)begin
//             if((y_counter >= ts-100))begin
//                 acq_ready=1;
//             end
//         end
//     end

// end

always@(posedge clk_vga)
begin
    wave1[tcnt]= sample1 * 4+100+vppset*100;
end

//闂堢姾绻栭柈銊ュ瀻鏉╂稖顢戦弰鍓с仛wave
always @(posedge clk_vga or negedge rst_n) 
begin        
    if(!rst_n)
    begin
        x_counter = 0;
        y_counter = 0;

    end
    else 
    begin
        //2---閸︹暆cq_ready==0鏉╂稖顢戦幍顐ｅ伎閸ф劖鐖ｉ敍灞芥倵閸欓绱伴張澶嬬壌閹诡喖娼楅弽鍥╂畱閺勫墽銇�
        if(1)begin
            if(x_counter==te-1)begin// 1055
                x_counter = 0;     
                if(y_counter == ts-1)  //623
                begin
                    y_counter = 0;
                end
                else 
                    y_counter = y_counter + 1;
            end
            else begin
                x_counter = x_counter + 1;
            end

        end
    end
end   





always @(x_counter or y_counter)                                         
begin
        //  if (x_counter<340)   colour<=12'b0010_0000_0000;
        //      else if (x_counter<440)    colour<=12'b0000_1000_0000;    //010
        //      else if (x_counter<540)    colour<=12'b0000_1001_0000;    //011
        //      else if (x_counter<640)    colour<=12'b0010_0000_0010;     //100
        //      else if (x_counter<740)    colour<=12'b0011_0000_0000;   //101
        //      else if (x_counter<840)    colour<=12'b1000_1000_1000;    //110
        //      else if (x_counter<940)    colour<=12'b0100_1000_0010;    //111 
        //      else   colour<=12'b0000_0000_0000 ; 
        
    if(600-y_counter==wave1[x_counter])
        begin
         colour<=12'b0000_1111_1111; 
        end
    else if(600-y_counter==wave2[x_counter])
        begin
         colour<=3'b110;
        end
    else
        begin
          if(x_counter==600) colour<=12'b1111_1111_1111;
          if(y_counter==300) colour<=312'b1111_1111_1111;
          if(x_counter==100 || x_counter==200 || x_counter==300 || x_counter==400 || x_counter==500 ||
            x_counter==700 || x_counter==800 || x_counter==900 || x_counter==1000 ||
            y_counter==100 || y_counter==200 || y_counter==400 || y_counter==500 || y_counter==600 )
            colour<=12'b0001_0001_0001;

          if(y_counter!=300&&x_counter!=600)
          colour<=12'b0000_0000_0000;
        end
        
      end    
      
      always@(posedge clk_vga)
      begin

//       wave[timeSer]= adcVal1 * 4+100+sw[2]*100;
//       wave_2[timeSer]= adcVal2 * 4+100+sw[1]*100;

      end
        assign  vgaRed=colour[11:8];
        assign  vgaGreen=colour[7:4];
        assign  vgaBlue=colour[3:0];
        assign Hsync = !(x_counter < ta);                                      
        assign Vsync = !(y_counter < to);   

reg [11:0] flag=0;
//always@(posedge acq_ready) begin
//    flag = flag +1;
//end


// reg cnt_reg=0;
// always @(posedge clk) cnt_reg <= ~cnt_reg;
// ila_1 u_ila_1 (
//     .clk(clk), // input wire clk
//     .probe0(sample1), // input wire [11:0]  probe0  
//     .probe1(wave1[500]), // input wire [11:0]  probe1 
//     .probe2(tcnt[11:0]), // input wire [11:0]  probe2 
//     .probe3(wave1[750])  ,   // input wire [11:0]  probe3
//     .probe4(30'b0)
// );


endmodule   
